The present invention relates to a nonvolatile semiconductor memory device and to a method for fabricating the same. At present, flash EEPROM (Electrically Erasable Programmable ROM) devices are used widely in electronic equipment as nonvolatile semiconductor memory devices which allow for electrical write and erase operations. The structures of memory cells in the nonvolatile semiconductor memory devices can be divided broadly into two types. The first one is a stacked-gate type having a multilayer electrode structure composed of a floating gate electrode and a control gate electrode which are stacked successively on a semiconductor substrate. The second one is a split-gate type having an electrode structure composed of a floating gate electrode and a control gate electrode which are disposed adjacent to each other in opposing relation to a channel region in a semiconductor substrate.
Referring to the drawings, a description will be given herein below to a conventional split-gate nonvolatile semiconductor memory device.
FIG. 42 shows a cross-sectional structure of a split-gate nonvolatile semiconductor memory device disclosed in U.S. Pat. No. 5,780,341, which has a stepped portion formed in a portion of a semiconductor substrate underlying a floating gate electrode. As shown in FIG. 42, a main surface of a semiconductor substrate 201 composed of, e.g., p-type silicon is formed with a stepped portion 205 composed of a first surface region 202 serving as an upper stage, a second surface region 204 serving as a lower stage, and a step side region 204 connecting the upper and lower stages.
A control gate electrode 210 is formed on the first surface region 202 of the stepped portion 205 with a gate insulating film 211 interposed therebetween. A floating gate electrode 212 formed to cover up the stepped portion 205 is capacitively coupled to the side surface of the control gate electrode 210 closer to the stepped portion and opposed to the second surface region 203 with a silicon dioxide film 213 serving as a tunnel film interposed therebetween.
A heavily doped n-type source region 221 is formed in the first surface region 202 of the semiconductor substrate 201, while a lightly doped n-type drain region 222a is formed in an area of the second surface region 203 underlying the floating gate electrode 212 and a heavily doped drain region 222b is formed externally of the lightly doped drain region 222a. 
In an area of the first surface region 202 underlying the floating gate electrode 212, a p-type impurity region 223 containing a p-type impurity at a concentration higher than in the semiconductor substrate 201 is formed. In such a structure, the floating gate electrode 212 is positioned in the direction in which electrons that have been injected into the heavily source region 221 flow so that the efficiency with which channel electrons are injected is improved.
As a result of conducting various studies including simulation and the like, the present inventors have concluded that the conventional split-gate nonvolatile semiconductor memory device is unsatisfactory in terms of the effect of increasing the efficiency of electron injection which is exerted by the stepped portion 205 formed in the semiconductor substrate 201.
When an electric field is applied during a write operation, a high electric field is hard to propagate upwardly from the lower corner of the stepped portion 205 in the source-side end portion of the lightly doped drain region 222a so that the localization of the electric field is likely to occur only in the vicinity of the lower corner of the stepped portion 205. As a result, a region where the electric field is intensest deviates to a lower portion from the step side region 204 into which the channel electrons from the floating gate electrode 212 are intended to be actually injected. The channel electrons flow directly to the lightly doped drain region 222a through a region at a distance from the step side region 204. This prevents the channel electrons from being injected into the floating gate electrode 212 with a sufficiently high efficiency.
During an erase operation, the electrons accumulated in the floating gate electrode 212 are extracted as a FN tunnel current to the heavily doped drain region 222b through a tunnel film composed of the portion of the silicon dioxide film 213 opposed to the floating gate electrode 212. With the increasing miniaturization of the element, however, the area of the portion of the tunnel film which permits the passage of the electrons is reduced so that the erase operation becomes difficult. For an easier erase operation, there is a method of enhancing the electric field applied to the tunnel film by increasing the drain voltage. In accordance with the method, however, holes having high energy (hot holes) generated in the heavily doped drain region 222b are generated simultaneously. The hot holes causes the problem that the reliability of the tunnel film is lowered or that the hot holes are captured in the tunnel film to degrade the characteristics of the element.
As the element is reduced in size, especially the gate length of the control gate electrode 210 is reduced, a short-channel effect, which is obscure in the conventional split-gate flash EEPROM device, is observed distinctly disadvantageously.
It is therefore a first object of the present invention to ensure, by solving the foregoing conventional problems, an improved efficiency with which electrons are injected into a nonvolatile semiconductor memory device having a stepped portion and allow a low-voltage and high-speed write operation.
A second object of the present invention is to increase an erase speed, while suppressing the occurrence of hot holes during an erase operation. A third object of the present invention is to allow miniaturization of an element by suppressing a short-channel effect.
To attain the first object, the present invention provides a nonvolatile semiconductor memory device having a stepped portion on the drain side, wherein a heavily doped impurity region of the conductivity type opposite to that of the drain region is formed at a position at a distance from and opposed to the upper corner of the stepped portion so as not to reach a first surface region and a step side region or adopts a method in which a proper substrate voltage is applied during a write operation.
To attain the second object, the present invention forms a drain region in which an impurity concentration is progressively higher with distance from a source region. To attain the third object, the present invention provides an impurity region of the conductivity type opposite to that of the source region such that the source region is covered with the impurity region.
Specifically, a first nonvolatile semiconductor memory device according to the present invention attains the first object and comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the first surface region; a control gate electrode formed on an area of the first surface region located in the vicinity of the stepped portion with the first insulating film interposed therebetween; a floating gate electrode formed on the semiconductor substrate so as to cover up the stepped portion, the floating gate electrode being capacitively coupled to a side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween and opposed to the second surface region with a third insulating film interposed therebetween; a source region formed in an area of the first surface region opposite to the floating gate electrode relative to the control gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and a depletion control layer formed in the semiconductor substrate to extend from a position located under the first surface region and at a distance from an upper corner of the stepped portion toward a lower corner of the stepped portion and adjoin the drain region without reaching the step side region, the depletion control layer being composed of a heavily doped impurity region of a conductivity type opposite to a conductivity type of the drain region.
The first nonvolatile semiconductor memory device is of a split-gate type comprising the depletion control layer which is formed within the semiconductor substrate and has the conductivity type opposite to that of the drain region. The arrangement prevents the depletion layer from extending to a region at a distance from the stepped portion during a write operation even when the drain region is provided in the second surface region serving as the lower stage of the stepped portion. In addition, a high electric field caused by the drain region is brought into a reverse-biased state due to the pn junction between the drain region and the depletion control layer and the potential difference across the pn junction is increased, so that a path of carriers flowing toward a high electron temperature region generated in the vicinity of the lower corner of the stepped portion is formed. This ensures an improved efficiency with which the electrons which have become hot electrons in the vicinity of the step side region are injected from the step side region into the floating gate electrode.
Preferably, the first nonvolatile semiconductor memory device further comprises a high-electric-field forming layer formed between the upper corner of the stepped portion and the depletion control layer, the high-electric-field forming layer being composed of an impurity region of the same conductivity type as the conductivity type of the depletion control layer. In the arrangement, an energy level in the step side region has a sharper gradient due to the pn junction portion composed of the interface between the high-electric-field forming layer and the drain region. As a result, a high electric field is generated at the interface between the high-electric-field forming layer and the drain region to overlap each of a high electric field caused by the stepped structure and a high electric field generated at the interface between the depletion control layer and the drain region, so that an electron temperature in the vicinity of the lower corner of the step side region is further increased. This increases the number of electrons in the channel that have become hot electrons and remarkably improves the efficiency with which the electrons are injected into the floating gate electrode.
In the first nonvolatile semiconductor memory device, an impurity concentration of the high-electric-field forming layer is preferably lower than an impurity concentration of the depletion control layer and higher than an impurity concentration of the semiconductor substrate. In the arrangement, the high-electric-field forming layer formed between the depletion control layer at a distance from the stepped portion and the stepped portion is depleted during a write operation so that the channel region is generated reliably in the vicinity of the step side region.
A second nonvolatile semiconductor memory device according to the present invention comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the semiconductor substrate so as to cover up the stepped portion; a floating gate electrode formed on the first insulating film so as to cover up the stepped portion; a control gate electrode formed on the floating gate electrode with the second insulating film interposed therebetween, the control gate electrode being capacitively coupled to the floating gate electrode; a source region formed in an area of the first surface region opposite to the stepped portion relative to the floating gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and a depletion control layer formed in the semiconductor substrate to extend from a position located under the first surface region and at a distance from an upper corner of the stepped portion toward a lower corner of the stepped portion and adjoin the drain region without reaching the step side region, the depletion control layer being composed of a heavily doped impurity region of a conductivity type opposite to a conductivity type of the drain region.
The second nonvolatile semiconductor memory device is of a stacked-gate type comprising the depletion control layer which is formed within the semiconductor substrate and has the conductivity type opposite to that of the drain region. The arrangement prevents the depletion layer from extending to a region at a distance from the stepped portion during a write operation even when the drain region is provided in the second surface region serving as the lower stage of the stepped portion. In addition, a high electric field is caused by the drain region at the pn junction between the drain region and the depletion control layer so that a path of carriers flowing toward a high electron temperature region generated in the vicinity of the lower corner of the stepped portion is formed. This ensures an improved efficiency with which the electrons which have become hot electrons in the vicinity of the step side region are injected from the step side region into the floating gate electrode.
Preferably, the second nonvolatile semiconductor memory device further comprises a high-electric-field forming layer formed between the upper corner of the stepped portion and the depletion control layer, the high-electric-field forming layer being composed of an impurity region of the same conductivity type as the conductivity type of the depletion control layer.
In this case, an impurity concentration of the high-electric-field forming layer is preferably lower than an impurity concentration of the depletion control layer and higher than an impurity concentration of the semiconductor substrate.
In the first or second nonvolatile semiconductor memory device, an end portion of the drain region closer to the source region is preferably located in the step side region without reaching the first surface region. In the arrangement, an area of the conductivity type opposite to that of the drain region is formed in the step side region so that the channel region is formed reliably by using the area as a depletion layer and an inversion layer.
In the first or second nonvolatile semiconductor memory device, the drain region preferably has at least three impurity regions formed to have respective impurity concentrations which are progressively higher with distance from the source region along a surface of the second surface region. In the arrangement, the area of the drain region opposite to the channel region is high in impurity concentration so that the intensity of an electric field in the area closer to the channel region is reduced relatively and the occurrence of hot holes in the peripheral region of the drain region during an erase operation is suppressed. This prevents the lowering of the reliability of a tunnel film and suppresses a short-channel effect as well, thereby attaining the second and third objects.
Preferably, the first or second nonvolatile semiconductor memory device further comprises an impurity region formed in the first surface region so as to cover a junction interface of the source region, the impurity region having a conductivity type opposite to a conductivity type of the source region to suppress a short-channel effect. The arrangement suppresses the expansion of the depletion layer in the channel region and suppresses the short-channel effect and a punch-through effect as well, thereby attaining the third object.
A third nonvolatile semiconductor memory device according to the present invention comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the first surface region; a control gate electrode formed on an area of the first surface region located in the vicinity of the stepped portion with the first insulating film interposed therebetween; a floating gate electrode formed on the semiconductor substrate so as to cover up the stepped portion, the floating gate electrode being capacitively coupled to a side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween and opposed to the second surface region with a third insulating film interposed therebetween; a source region formed in an area of the first surface region opposite to the floating gate electrode relative to the control gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and an impurity region formed in the semiconductor substrate to be located in the vicinity of an corner between the first surface region and the step side region, the impurity region having an impurity concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity type of the drain region, the drain region having at least three impurity diffusion regions formed to have respective impurity concentrations which are progressively higher with distance from the source region along a surface of the second surface region.
The third nonvolatile semiconductor memory device is of a split-gate type comprising an impurity region which is formed within the semiconductor substrate to be located in the vicinity of the corner between the first surface region and the step side region and has the conductivity type opposite to that of the drain region. As a result, a high electric field is generated at the pn junction interface between the impurity region and the drain region and the number of electrons in the channel that have become hot electrons is increased, which improves the efficiency with which the electrons are injected into the floating gate electrode. The third nonvolatile semiconductor memory device also has at least three impurity diffusion regions formed to have respective impurity concentrations which are progressively higher with distance from the source region along the surface of the second surface region. This relatively reduces the intensity of an electric field in the area of the drain region closer to the channel region and suppresses the occurrence of hot holes in the area of the drain region located around the channel during an erase operation and suppresses the short-channel effect as well.
A fourth nonvolatile semiconductor memory device according to the present invention comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the first surface region; a control gate electrode formed on an area of the first surface region located in the vicinity of the stepped portion with the first insulating film interposed therebetween; a floating gate electrode formed on the semiconductor substrate so as to cover up the stepped portion, the floating gate electrode being capacitively coupled to a side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween and opposed to the second surface region with a third insulating film interposed therebetween; a source region formed in an area of the first surface region opposite to the floating gate electrode relative to the control gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; a first impurity region formed in the semiconductor substrate to be located in the vicinity of an corner between the first surface region and the step side region, the impurity region having an impurity concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity type of the drain region; and a second impurity region formed in the first surface region so as to cover a junction interface of the source region, the second impurity region having a conductivity type opposite to a conductivity type of the source region to suppress a short-channel effect.
The fourth nonvolatile semiconductor memory device is of a split-gate type comprising the first impurity region which is formed within the semiconductor substrate to be located in the vicinity of the corner between the first surface region and the step side region and has a conductivity type opposite to that of the drain region. As a result, a high electric field is generated at the pn junction interface between the first impurity region and the drain region and the number of electrons in the channel that have become hot electrons is increased, which improves the efficiency with which the electrons are injected into the floating gate electrode. The fourth nonvolatile semiconductor memory device also has the second impurity region formed to cover the junction interface of the source region and having a conductivity type opposite to that of the source region. This suppresses the expansion of the depletion layer in the channel region and suppresses the short-channel effect and the punch-through effect as well. A fifth nonvolatile semiconductor memory device according to the present invention comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the semiconductor substrate so as to cover up the stepped portion; a floating gate electrode formed on the first insulating film so as to cover up the stepped portion; a control gate electrode formed on the floating gate electrode with the second insulating film interposed therebetween, the control gate electrode being capacitively coupled to the floating gate electrode; a source region formed in an area of the first surface region opposite to the stepped portion relative to the floating gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and an impurity region formed in the semiconductor substrate to be located in the vicinity of an corner between the first surface region and the step side region, the impurity region having an impurity concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity type of the drain region, the drain region having at least three impurity diffusion regions formed to have respective impurity concentrations which are progressively higher with distance from the source region along a surface of the second surface region.
The fifth nonvolatile semiconductor memory device is of a stacked-gate type comprising an impurity region which is formed within the semiconductor substrate to be located in the vicinity of the corner between the first surface region and the step side region and has the conductivity type opposite to that of the drain region. As a result, a high electric field is generated at the pn junction interface between the impurity region and the drain region and the number of electrons in the channel that have become hot electrons is increased, which improves the efficiency with which the electrons are injected into the floating gate electrode. The third nonvolatile semiconductor memory device also has at least three impurity diffusion regions formed to have respective impurity concentrations which are progressively higher with distance from the source region along the surface of the second surface region. This relatively reduces the intensity of an electric field in the area of the drain region closer to the channel region and suppresses the occurrence of hot holes in the area of the drain region located around the channel during an erase operation and suppresses the short-channel effect as well.
A sixth nonvolatile semiconductor memory device according to the present invention comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the semiconductor substrate so as to cover up the stepped portion; a floating gate electrode formed on the first insulating film so as to cover up the stepped portion; a control gate electrode formed on the floating gate electrode with the second insulating film interposed therebetween, the control gate electrode being capacitively coupled to the floating gate electrode; a source region formed in an area of the first surface region opposite to the stepped portion relative to the floating gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; a first impurity region formed in the semiconductor substrate to be located in the vicinity of an corner between the first surface region and the step side region, the impurity region having an impurity concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity type of the drain region; and a second impurity region formed in the first surface region so as to cover a junction interface of the source region, the second impurity region having a conductivity type opposite to a conductivity type of the source region to suppress a short-channel effect.
The sixth nonvolatile semiconductor memory device is of a stacked-gate type comprising the first impurity region which is formed within the semiconductor substrate to be located in the vicinity of the corner between the first surface region and the step side region and has a conductivity type opposite to that of the drain region. As a result, a high electric field is generated at the pn junction interface between the first impurity region and the drain region and the number of electrons in the channel that have become hot electrons is increased, which improves the efficiency with which the electrons are injected into the floating gate electrode. The sixth nonvolatile semiconductor memory device also has the second impurity region formed to cover the junction interface of the source region and having a conductivity type opposite to that of the source region. This suppresses the expansion of the depletion layer in the channel region and suppresses the short-channel effect and the punch-through effect as well.
In any one of the first to sixth nonvolatile semiconductor memory devices, a substrate voltage is preferably applied to the semiconductor substrate such that a channel region in which carriers flow from a portion of the first surface region underlying the floating gate electrode toward the step side region is formed. In the arrangement, a potential at the floating gate is relatively increased in the portion of the semiconductor substrate enclosed with the first surface region and the step side region so that the carriers are strongly attracted to the surface of the semiconductor substrate. In addition, the current density is increased only during the application of the substrate voltage so that power consumption while a write operation is not performed is reduced significantly.
In any one of the first to sixth nonvolatile semiconductor memory devices, a specified drain voltage and a specified control gate voltage are preferably applied to the drain region and to the control gate electrode, respectively, such that a channel region in which carriers flow from a portion of the first surface region underlying the floating gate electrode toward the step side region is formed.
A seventh nonvolatile semiconductor memory device according to the present invention comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the first surface region; a control gate electrode formed on an area of the first surface region located in the vicinity of the stepped portion with the first insulating film interposed therebetween; a floating gate electrode formed on the semiconductor substrate so as to cover up the stepped portion, the floating gate electrode being capacitively coupled to a side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween and opposed to the second surface region with a third insulating film interposed therebetween; a source region formed in an area of the first surface region opposite to the floating gate electrode relative to the control gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and an impurity region formed in the first surface region and step side region of the semiconductor substrate to have an impurity concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity type of the drain region, wherein a substrate voltage is applied to the semiconductor substrate such that a channel region in which carriers flow from a portion of the first surface region underlying the floating gate electrode toward the step side region is formed.
The seventh nonvolatile semiconductor memory device is of a split-gate type in which, even if a depletion control layer is not provided in a portion of the semiconductor substrate at a distance from the step side region of the stepped portion, a potential at the floating gate electrode over the portion of the semiconductor substrate enclosed with the first surface region and the step side region is increased relatively by applying, e.g., a substrate voltage of a polarity opposite to that of the drain voltage during a write operation, i.e., by applying a negative substrate voltage in the case of an n-type channel and applying a positive substrate voltage in the case of a p-type channel. As a result, the carriers are strongly attracted to the surface of the semiconductor substrate so that the efficiency with which the carriers are injected into the floating gate electrode is improved.
An eighth nonvolatile semiconductor memory device according to the present invention comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the semiconductor substrate so as to cover up the stepped portion; a floating gate electrode formed on the first insulating film so as to cover up the stepped portion; a control gate electrode formed on the floating gate electrode with the second insulating film interposed therebetween, the control gate electrode being capacitively coupled to the floating gate electrode; a source region formed in an area of the first surface region opposite to the stepped portion relative to the floating gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and an impurity region formed in the first surface region and step side region of the semiconductor substrate to have an impurity concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity type of the drain region, wherein a substrate voltage is applied to the semiconductor substrate such that a channel region in which carriers flow from a portion of the first surface region underlying the floating gate electrode toward the step side region is formed.
The eighth nonvolatile semiconductor memory device is of a stacked-gate type in which, even if a depletion control layer is not provided in a portion of the semiconductor substrate at a distance from the step side region of the stepped portion, a potential at the floating gate electrode over the portion of the semiconductor substrate enclosed with the first surface region and the step side region is increased relatively by applying a negative substrate voltage in the case of an n-type channel and applying a positive substrate voltage in the case of a p-type channel. As a result, the carriers are strongly attracted to the surface of the semiconductor substrate so that the efficiency with which the carriers are injected into the floating gate electrode is improved.
A first method for fabricating a nonvolatile semiconductor memory device according to the present invention comprises: a first step of forming a control gate electrode on a semiconductor substrate with a first insulating film interposed therebetween; a second step of masking a region of the semiconductor substrate to be formed with a source, ion-implanting a high-concentration impurity of a first conductivity type into the semiconductor substrate by using the control gate electrode as a mask, and thereby forming a heavily doped impurity region; a third step for forming a sidewall composed of an insulating film on a side surface of the gate electrode, etching the semiconductor substrate by using the formed sidewall and the control gate electrode as a mask and masking the source formation region, and thereby forming a recessed portion in the semiconductor substrate, while forming, in the semiconductor substrate, a stepped portion composed of a first surface region in which a portion of the semiconductor substrate underlying the sidewall serves as an upper stage, a second surface region in which a bottom surface of the recessed portion serves as a lower stage, and a step side region connecting the upper and lower stages; a fourth step of selectively ion-implanting a low-concentration impurity of a second conductivity type into the second surface region of the semiconductor substrate and thereby forming a lightly doped drain region of the second conductivity type in the second surface region, while inverting a conductivity type of each of portions of the heavily doped impurity region located in the vicinity of the first surface region, an upper corner of the stepped portion, and the step side region of the stepped portion and thereby forming a depletion control layer composed of the heavily doped impurity region and located discretely at a distance from the first surface region and the step side region to adjoin the lightly doped drain region; a fifth step of removing the sidewall and forming a second insulating film over the side surface of the control gate electrode closer to the stepped portion, the first surface region, the step side region, and the second surface region; a sixth step of depositing a conductor film over the entire surface of the second insulating film, etching the deposited conductor film, and thereby forming by self alignment a floating gate electrode covering up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with the second insulating film interposed therebetween, and opposed to the second surface region with the second insulating film interposed therebetween; and a seventh step of ion-implanting an impurity of the second conductivity type into the semiconductor substrate by using the control gate electrode and the floating gate electrode as a mask and thereby forming a source region of the second conductivity type in the first surface region, while forming a drain region of the second conductivity type in the second surface region.
The first method for fabricating a nonvolatile semiconductor memory device comprises the step of selectively ion-implanting the low-concentration impurity of the second conductivity type into the second surface region composed of the bottom surface of the recessed portion in the semiconductor substrate and thereby forming the lightly doped drain region of the second conductivity type in the second surface region, while inverting the conductivity type of each of the portions of the heavily doped impurity region located in the vicinity of the first surface region, the upper corner of the stepped portion, and the step side region of the stepped portion and thereby forming the depletion control layer composed of the heavily doped impurity region of the first conductivity type and located distinctly at a distance from the first surface region and the step side region to adjoin the lightly doped drain region. This ensures the fabrication of the first nonvolatile semiconductor memory device according to the present invention.
In the first method for fabricating a nonvolatile semiconductor memory device, the second step preferably includes the step of: ion-implanting again an impurity of the first conductivity type into the heavily doped impurity region that has been formed and thereby forming another impurity region of the first conductivity type which is shallower in diffusion depth than the heavily doped impurity region and the fourth step includes the step of: forming a high-electric-field forming layer composed of the other impurity region between an upper corner of the stepped portion and the depletion control layer.
Preferably, the first method for fabricating a nonvolatile semiconductor memory device further comprises, after the seventh step: an eighth step of depositing a third insulating film on the floating gate electrode, ion-implanting an impurity of the second conductivity type into the semiconductor substrate by using the deposited third insulating film and the floating gate electrode as a mask, and thereby forming, in the second surface region, a heavily doped drain region of the second conductivity type which is higher in impurity concentration than the drain region. This ensures the fabrication of the third nonvolatile semiconductor memory device according to the present invention.
Preferably, the first method for fabricating a nonvolatile semiconductor memory device further comprises, after the fourth step, the step of: masking a region extending from the control gate electrode to the second surface region and forming, in the source formation region, an impurity region of the first conductivity type which is deeper in diffusion depth than the source region. This ensures the fabrication of the fourth nonvolatile semiconductor memory device according to the present invention.
A second method for fabricating a nonvolatile semiconductor memory device according to the present invention comprises: a first step of selectively ion-implanting a high-concentration impurity of a first a conductivity type into a region of a semiconductor substrate to be formed with a drain and thereby forming a heavily doped impurity region of the first conductivity type; a second step of selectively etching the heavily doped impurity region except for an end portion thereof closer to a region of the semiconductor substrate to be formed with a source and thereby forming a recessed portion in the semiconductor substrate, while forming, in the semiconductor substrate, a stepped portion composed of a first surface region in which the end portion of the heavily doped impurity region serves as an upper stage, a second surface region in which a bottom surface of the recessed portion serves as a lower stage, and a step side region connecting the upper and lower stages; a third step of selectively ion-implanting a low-concentration impurity of a second conductivity type into the second surface region of the semiconductor substrate and thereby forming a lightly doped drain region of the second conductivity type in the second surface region, while inverting a conductivity type of each of portions of the heavily doped impurity region located in the vicinity of the first surface region, an upper corner of the stepped portion, and the step side region of the stepped portion and thereby forming a depletion control layer composed of the heavily doped impurity region and located discretely at a distance from the first surface region and the step side region to adjoin the lightly doped drain region; a fourth step of successively forming a first insulating film, a floating gate electrode, a second insulating film, and a control gate electrode on the semiconductor substrate such that the stepped portion is covered up therewith; and a fifth step of ion-implanting an impurity of the second conductivity type into the semiconductor substrate by using the control gate electrode as a mask and thereby forming a source region of the second conductivity type in the source formation region, while forming a drain region of the second conductivity type in the drain formation region.
The second method for fabricating a nonvolatile semiconductor memory device comprises the step of selectively ion-implanting the low-concentration impurity of the second conductivity type into the second surface region of the semiconductor substrate and thereby forming the lightly doped drain region of the second conductivity type in the second surface region, while inverting the conductivity type of each of the portions of the heavily doped impurity region of the first conductivity type located in the vicinity of the first surface region, the upper corner of the stepped portion, and the step side region of the stepped portion and thereby forming the depletion control layer composed of the heavily doped impurity region and located distinctly at a distance from the first surface region and the step side region to adjoin the lightly doped drain region. This ensures the fabrication of the second nonvolatile semiconductor memory device according to the present invention.
In the second method for fabricating a nonvolatile semiconductor memory device, the first step preferably includes the step of: ion-implanting again an impurity of the first conductivity type into the heavily doped impurity region that has been formed and thereby forming another impurity region of the first conductivity type which is shallower in diffusion depth than the heavily doped impurity region and the third step includes the step of: forming a high-electric-field forming layer composed of the other impurity region between an upper corner of the stepped portion and the depletion control layer.
Preferably, the second method for fabricating a nonvolatile semiconductor memory device further comprises, after the fifth step: a sixth step of depositing a third insulating film on the control gate electrode, etching the deposited third insulating film, and thereby forming sidewalls on respective side surfaces of the floating gate electrode and the control gate electrode; and a seventh step of ion-implanting an impurity of the second conductivity type into the semiconductor substrate by using the control gate electrode and the sidewalls as a mask and thereby forming, in the second surface region, a heavily doped drain region of the second conductivity type which is higher in impurity concentration than the drain region. This ensures the fabrication of the fifth nonvolatile semiconductor memory device according to the present invention.
Preferably, the second method for fabricating a nonvolatile semiconductor memory device further comprises, after the third step, the step of: masking a region extending from the control gate electrode to the second surface region and forming, in the source formation region, an impurity region of the first conductivity type which is deeper in diffusion depth than the source region. This ensures the fabrication of the sixth nonvolatile semiconductor memory device according to the present invention.